The invention relates to high voltage semiconductor devices and the manufacturing process thereof and in particular, to modular techniques for adding high voltage devices to an existing process flow for semiconductor devices.
Devices having higher voltage rating than existing devices are often required to be integrated on a chip of existing device to satisfy the demand of new applications. In many cases such integration of higher voltage device into existing lower voltage device requires drastic change to the proven process flow and/or conditions for manufacturing the existing lower voltage device resulting in performance deterioration of the existing lower voltage device to a degree that device models will have to be updated. To avoid the long design cycle and high cost of product development, efforts have been focused on techniques that require only minor change to the existing low voltage device process conditions thus minimize the impact to the performance of existing lower voltage device.
Generally in BCD or BiCMOS technologies, the highest operating voltage is controlled by reach-through breakdown of a vertical structure of P to N junction. This vertical junction breakdown is a function of Epi thickness and doping density. FIG. 1 shows an example of an existing device 300 formed in a semiconductor chip comprising an n-epitaxial layer 18 having a thickness 43 disposed on a P substrate 14 having a resistivity of 11 to 15 Ohms-cm. Without showing the detail structure of the device 300, a number of N-wells 22, 24 and P-wells 26, 48 are provided in the N-Epi layer. Buried P regions 46 extend from the bottoms of edge P-well 48 into the substrate layer 14 providing isolation of the device 300 from the rest area of the semiconductor chip where other devices may be formed. Device 300 further comprises a N buried region 35 under the P-well 26 to limit the maximum operation voltage of the device 300. Using a 5 um Epi layer 18 and controlling the depth 45 of P-well 26 to optimize the performance of device 300, the vertical space 47 between the bottom of P-well 26 and the top of buried N region 35 limits a vertical breakdown voltage at around 70V therefore limit the device 300 operates under 70V when a lateral breakdown controlling factor 49, namely the lateral distance between the buried P regions 46 and the N buried region 35, is large enough that a lateral breakdown voltage is much higher than the vertical breakdown voltage. The manufacturing process would start with the substrate layer 14 then implant ions for regions 35 and 46 to be formed respectively in later steps. The epitaxial layer 18 is then disposed on top of the substrate layer 14 and multiple N-wells and P-wells are formed extending downwards from a top surface of the epitaxial layer. Additional steps may be carried out to form a specific function such as a bipolar transistor or a MOSFET. In the case a higher operation voltage device is required to be integrated in a separate area on the same chip, one method to increase P to N vertical breakdown voltage is to increase the thickness of Epi layer 18. This will affect the performance and isolation of existing device 300 if the process and condition of making device 300 remain the same.
Another method is introducing a lighter doping layer to reduce the dopant concentration. For example, in United States patent publication number US2004/0113204 Hideaki Tsuchiko discloses an integrated circuit that includes a high voltage Schottky barrier diode and a low voltage device. The Schottky barrier diode includes a lightly doped p-well as a guard ring while the low voltage devices are built using standard, more highly doped p-wells. By using a process including lightly doped p-wells and standard p-wells, high voltage and low voltage devices can be integrated onto the same integrated circuit. Although the Schottky barrier diode built in the lightly doped P-well increases its breakdown voltage to 120V from 80V when built in a standard doped P-well, the example showing in FIG. 1 can only increase breakdown voltage about 0-20V.
Combination of both methods and device layout enable integrating high and low voltage devices on the same chip. However, these methods often have a minor affect to existing device performances. Some devices require a minor tweak to SPICE models. Therefore it is highly desirable to develop new techniques to integrate a high voltage device into a low voltage chip that require only inserting a few steps to existing low voltage process flow to add higher voltage devices onto the low voltage device chip yet without impacting the performance of the low voltage device.